A Low Power and High-Speed Reconfigurable Routing Topology for 2D-Multi-Processor System on Chip

Abstract

Multiprocessor system on chip (MPSoC) technology is widely used in various applications due to its capacity of delivering the superior performance at the low power cost. The System-on-Chips (SoCs) technique is generally used in consumer electronics with the integration of multiple functionalities of the high-end processors embedded on a common platform. The major challenge encountered by the MPSoC architecture is a higher delay in the data transmission, which is caused due to the network congestion between the nodes. In order to overcome this, an effective network topology with an adequate routing is required to be developed, to achieve a better performance in the MPSoC. The mesh topology is integrated with the torus topology to achieve an optimal routing of the data packets from the source to the destination router of MPSoC. In addition, the lightweight XY-YX routing is accomplished over the MPSoC network topology, to obtain the shortest path through the MPSoC networks. The prediction of the response packet path has been used in this proposed work, to minimize the delay during the data transmission. The design of MPSoC architecture is developed in the Xilinx ISE 14.2 software and validated with successful implementation on various Field Programmable Gate Array (FPGA) families. The performance of the proposed MPSoC architecture with hybrid network topology has been analyzed in terms of Look Up Table (LUT), slices, flip flops, delay, frequency and power. Also, the performance of the proposed MPSoC architecture has been compared with three existing architectures MXY-SoC, K Means-MPSoC and SDMPSoC. The number of LUTs used by the proposed MPSoC architecture is 1326 for Virtex 6, which is less than that of used by MXY-SoC architecture.