Energy Efficient Parallel Adder With Faithful Approximation And Reversible Logic For Digital Image Processing

Abstract

Reversible CMOS designs have been emerging to replace the conventional digital
computers and found to be the promising technology to improve circuit performance in terms
of power, speed, heat dissipation, life span, input traceability, etc. In this approach, we propose
a high-speed fault-tolerant parallel adder with faithful approximation using reversible logic. In
the proposed reversible adder, n bit input is grouped into m bit blocks and parallel addition is
performed in n/m blocks using the carry select addition algorithm. Further more, delay
balanced reversible parallel carry(DBRPC) logic is proposed and used to reduce delay at the
block level. Approximate PC logic is used in the least n/2m blocks and exact DBRPC logic is
used to design most n/2m blocks. As an enhancement to the Proposed Reversible Parallel
Faithful approximate Adder(P-RPFA) in terms of area, approximate addition is replaced with
simple OR logic. Evaluations reveal that approximation of least n/2 bits in P-RPFA and its area
enhanced version(P-RPFAAE) introduce a maximum error of 1 Unit at Bit Position(UBP) n/2.
Evaluations revealed that the quantum cost of the P-RPFAAE design is 30.4% less compared to
the P-RPFA design. Synthesis results of the P-RPFA and P-RPFAAE designs using Cadence
Encounter with 90 nm ASIC technology for n=16, m=4 demonstrated 57.3% &60.4%PowerDelay Product(PDP) reductions respectively when compared to the conventional reversible
counterpart.