Low Power Adder Architectures and its Power Analysis using 45 NM CMOS Technology

  • K. Dhanumjaya, Dr. M. N. Giri Prasad


This paper describes the design of a 45nm CMOS technology Adder architectures for highly energy-efficient applications of embedded processors. Design of Ripple Carry Adder (RCA), Carry Look- ahead Adder (CLA) and Carry Select Adder (CSA) is present in this paper, to improve the speed and power. The comparative analysis of Adder Architectures is presented. Average power, Static Power and Delay are the parameters evaluated using Cadence tool. For a full-chip implementation of low-power systems operating at ultra-low voltage is feasible. The average power is extracted for logic cells at supply voltages 1.0 V at different frequencies.