An Efficient Diagnosis Pattern Generation Procedure for Multi Faults in Digital Circuits

Authors

  • Naga Ganesh, Madhava Rao Alla, D. Manaswi, K. Kiran

Abstract

In this paper, an efficient diagnosis pattern generation procedure for multi faults in digital circuits is implemented. Basically, fault diagnosis plays very important role in VLSI testing procedures. There are different types of faults are used in VLSI (Very Large Scale Integration) but the two commonly used faults in this paper are bridging and stuck at faults. Without altering the circuit under test, both faults stuck-at and bridging are distinguished based on the creation of pattern generation procedure. ATPG tools are used between two faults which are generated from test patterns. Undistinguished fault pairs identification unit will allow to embed the all fault pairs which are undistinguished. Multi-pair diagnostic ATPG method will use the grouping for fault pairs and next it will switch the cells from the group and at last test generation is applied for the group. Hence, from results it can observe that diagnosis pattern generation procedure for multi faults in digital circuits reduces the faults, delay, power and area in effective way.

Published

2020-11-01

Issue

Section

Articles