Design of Power optimized Pipelined 64 – bit Mini Instruction Set Programmable Processor (MISPP)

Abstract

Low Power designs are necessary for the VLSI Integrated circuits because, it has to fulfill all critical parameters such as, the performance,  speed, compactness, portability (battery size and battery life), and better functionality in the design [1][2].  For a good IC design, critical parameters like power, area, speed and delay are to be handled carefully so as to achieve high performance [7]. Once the technology and supply voltage have been fixed, major power  savings can be done through careful reduction of switching activity. Most of the current processors are having so many feasible features but at the same time consuming power also. In the proposed architecture, pipe line concepts are introduced along with dynamic power management techniques proposed to optimize the power. It is working with less number of instructions.

The designed processor (MISPP)   utilizes the device elements to balance speed and power.  Along   with   the other  power  reduction  techniques, low power, and  high performance devices in MISPP  accomplished  the pipeline process with  minimum  delay and  great  throughput. In a comparative study, MISPP frequency (758.044 MHz) has been enhanced by 2.438 times of the nearest counterpart (310.828).  The least delay is noted to complete the pipeline process.

Keywords- MISPP; Dynamic Power Management; Power; Delay; Pipeline