Design of Phase Locked Loop (PLL) using CMOS Technology

Authors

  • Narmadha G, Haarindra Prasad, Nivetha K, Raman Raguraman, Manickam.R, Deivasigamani

Abstract

Phase Locked Loop (PLL) acts a vital function in the development of electronic goods for wireless communication. There is a need for a PLL circuit with greater locking efficiency due to an increase in the speed of operation of the circuit. Phase Locked Loops is primarily used for synchronization, frequency translation, AM detection, FM demodulation, Frequency shift keying Demodulator, clock synthesis and jitter reduction in mobile or wireless communications. In this paper, PLL is designed for digital signal processing with a faster locking variety using 0.12 ?m CMOS technology. Here, the frequency is locked in less time. This PLL circuit has a wide range of applications in modern communication.

Keywords- Synchronization, PLL and VCO

Published

2020-12-17

Issue

Section

Articles