Analysis of Sneak Path Issues in Memristor Based 4x4 And 8x8 Crossbar Nonvolatile Random Access Memory Array

Authors

  • Dr. V. Saminathan, Dr. V. Sampathkumar, Dr. P. Sridharan

Abstract

Numerous memory vendors are pursuing different categories of memory cells that can deal with more density, nonvolatility, extreme performance and long endurance. There are a number of on-going determinations to architect main memory systems with these novel NVRAMs that can contest with traditional DRAM and SRAM systems. Every NVRAM has individualities that entail novel micro architectures and procedures for memory access. Resistive memories have commonly been premeditated as substitutes for level two and secondary level caches because of their low leakage energies. In this paper, we examine a memristor-CMOS based nonvolatile random access 4x4 and 8x8 memory array and also investigate the sneak path problem. It can be evaluated by introducing three types of array structure such as grounded array, floating array and gated array structure. Furthermore, the sneak current, noise margin and power consumption of the proposed array structures related to these solutions can be evaluated during different memory operations.

Published

2020-11-01

Issue

Section

Articles