Development of an Integration Script and a HTML Table Summary for different checkers

Abstract

Design Verification has to be done after designing. This can save a company a lot of money if performed. It is done before manufacturing. The design flow shows that there are three main steps that have to be followed so that an IC or a chip can be given to a customer. They are design, verification and testing. The design is first made that is the RTL design. Integration technologies have advanced across the years. But with functionality in mind that is for the rise of it, design problem has arisen and it is also complex. So after this, verification is done which is used to check how correct a design is with respect to its functionality. Then after this, testing is done. When all of these steps have been performed, then the IC or chip can be given to the customer. In this paper, an integration script and a HTML table summary has been implemented for the different checkers Report force, Report version, Report config label, Coverage report, Jira Issues and Label Sanity. The execution times obtained for the different checkers are 2.2s for Sync to Label and Check, 3s for Report Force, 3.3s for Report Version, 3.6s for Report Config Label, 2.7s for Coverage Report, 2.5s for Jira Issues and 50s for Label Sanity.