Design Of Low Power 2 To 1 Multiplexer Using Transistor Stacking Technique

Abstract

Power optimization is one among the most VLSI designer’s goals. Reduced power consumption is particularly advisable for battery durability of mobile device such as laptop, PDA and mobile phone. The major challenge of VLSI designers is reduction energy consumption without increasing the switching time. Various methods have been suggested for efficiently minimize the power consumption such as body biasing, MTCMOS, transistor stacking technique.

In this paper, the power dissipation of 2 to 1 multiplexer is analyzed with and without the transistor stacking technique. The power evaluation has been carried out using extensive simulation on LTspice circuit simulator. The simulation result shows the validity of the transistor stacking technique. The power consumption is from 56% to 60% less than conventional approach.

Keywords- 2:1mux; CMOS technology; leakage current; power consumption; optimization; transistor stacking technique.